a1. Versatile Interface Adapter brief reference (from Synertek data sheet) ----------------------------------------------- Features: - two 8-bit bidirectional I/O ports - two 16-bit programmable Timer/counters - serial data port - CMOS compatible peripheral port A lines - expanded handshake capability allows positive control of data transfers between processor and peripheral devices - latched output and input registers Peripheral A port (PA0-PA7): It consists of 8 lines which can be individually programmed to act as inputs or outputs under control of a Data Direction Register. The polarity of output pins is controlled by an Output Register and input data may be latched into an internal register under control of the CA1 line. Peripheral A Control Lines (CA1,CA2): The two peripheral A control lines act as interrupt inputs or as handshake outputs. Each line controls an internal interrupt flag with a corresponding interrupt enable bit. In addition, CA1 controls the latching of data on peripheral A port input lines (CA1 is an input only) Peripheral B port (PB0-PB7): It consists of eight bi-directional lines which are controlled by an output register and a data direction register in much the same manner as the PA port. In addition, the PB7 output signal can be controlled by one of the interval timers while the second timer can be programmed to count pulses on the PB6 pin. Peripheral B Control Lines (CB1,CB2): They act as interrupt inputs or as handshake outputs. As with CA1 and CA2, each line controls an interrupt flag with a corresponding interrupt enable bit. In addition, these lines act as a serial port under control of the Shift Register. Registers Reading/writing registers of the chip allows to control the powerful features. A register is read or written when the chip is selected and the low four address bits indicate the desired register: Address Reg Description (Write) | (Read) ---------------------------------------------------------------- 0000 ORB/IRB Output Register B | Input Register B 0001 ORA/IRA Output Register A | Input Register A 0010 DDRB Data Direction Register B 0011 DDRA Data Direction Register A 0100 T1C-L T1 low-order Latches | T1 low-order Counter 0101 T1C-H T1 high-order Counter 0110 T1L-L T1 low-order Latches 0111 T1L-H T1 high-order Latches 1000 T2C-L T2 low-order Latches | T2 low-order Counter 1001 T2C-H T2 high-order Counter 1010 SR Shift Register 1011 ACR Auxiliary Control Register 1100 PCR Peripheral Control Register 1101 IFR Interrupt Flag Register 1110 IER Interrupt Enable Register 1111 ORA/IRA Same as reg 1 except no handshake Port A and Port B operation: Each 8-bit peripheral port has a Data Direction Register (DDRA, DDRB) for specifying whether the peripheral pins are to act as inputs or outputs. A 0 in a bit of the Data Direction Register causes the corresponding peripheral pin to act as an input. A 1 causes the pin to act as an output. When programmed as an output each peripheral pin is also controlled by a corresponding bit in the Output Register (ORA, ORB). A 1 in the Output Register causes the output to go high, and a 0 causes the output to go low. Data may be written into Output Register bits corresponding to pins which are programmed as inputs. In this case, however, the output signal is unaffected. Reading a peripheral port causes the contents of the Input Register (IRA, IRB) to be transferred onto the data bus. With input latching disabled, IRA will always reflect the levels on the PA pins. With input latching enabled and the selected active transition on CA1 having occurred, IRA will contain the data present on the PA lines at the time of the transition. Once IRA is read, however, it will appear transparent and will reflect the current state of the PA lines until the next latching transition. The IRB register operates similar to the IRA register. However, for pins programmed as outputs, there is a difference. When reading IRA, the level on the pin determines whether a 0 or a 1 is sensed. When reading IRB, however, the bit stored in the output register, ORB, is the bit sensed. Finally, the 6522 allows positive control of data transfers between the system processor and peripheral devices through the operation of handshakes lines. Port A lines (CA1, CA2) handshake data on both a read and a write operation while the Port B lines (CB1, CB2) handshake on a write operation only. Read Handshake The peripheral device must generate the equivalent of a "data ready" signal to the processor signifying that valid data is present on the peripheral port. This signal normally interrupts the processor, which then reads the data, causing generation of a "data taken" signal. Automatic read handshaking is possible on the peripheral A port only. The CA1 interrupt input pin accepts the "data ready" signal and CA2 generates the "data taken" signal. The "data ready" signal will set an internal flag which may interrupt the processor or which may be polled under program control. The "data taken" signal can either be a pulse or a level which is set low by the system processor and is cleared by the "data ready" signal. Write Handshake For write handshaking, the 6522 generates the "data ready" signal and the peripheral device must respond with the "data taken" signal. This can be accomplished on both the PA port and the PB port. CA2 or CB2 act as a "data ready" output in either the handshake mode or pulse mode and CA1 or CB1 accept the "data taken" signal from the peripheral device, setting the interrupt flag and cleaning the "data ready" output. Selection of operating modes for CA1, CA2, CB1 and CB2 is accomplished by the Peripheral Control Register. Peripheral Control Register bit 0: CA1 interrupt control 0 = negative active edge 1 = positive active edge bits 321: CA2 control 000 = input, negative active edge 001 = independant interrupt input, negative edge 010 = input, positive active edge 011 = independent interrupt input, positive edge 100 = handshake output 101 = pulse output 110 = low output 111 = high output bit 4: CB1 interrupt control 0 = negative active edge 1 = positive active edge bits 765: CB2 control 000 = input, negative active edge 001 = independant interrupt input, negative edge 010 = input, positive active edge 011 = independent interrupt input, positive edge 100 = handshake output 101 = pulse output 110 = low output 111 = high output Timer operation: Interval timer T1 consists of two 8-bit latches and a 16-bit counter. The latches are used to store data which is to be loaded into the counter. After loading, the counter decrements at 02 (Phi-2) clock rate. Upon reaching zero, an interrupt flag will be set, and an IRQ will be raised if the interrupt is enabled. The timer will then disable any further interrupts, or (when programmed to) will automatically transfer the contents of the latches into the counter and begin to decrement again. In addition, the timer may be programmed to invert the output signal on a peripheral pin each time it times-out. Two bits are provided in the Auxiliary Control Register (bits 6 and 7) to allow selection of the T1 operating modes. Auxiliary Control Register bit 0: Port A Latch enable 0 = disable 1 = enable latching bit 1: Port B Latch enable 0 = disable 1 = enable latching bits 432: Shift Register Control 000 = disabled 001 = shift in under control of T2 010 = shift in under control of 02 011 = shift in under control of external clock 100 = shift out free-running at T2 rate 101 = shift out under control of T2 110 = shift out under control of 02 111 = shift out under control of external clock bit 5: T2 timer control 0 = timed interrupt 1 = count down with pulses on PB6 bits 76: T1 timer control 00 = timed interrupt each time T1 is loaded, PB7 disabled 01 = continuous interrupts, PB7 disabled 10 = timed interrupt each time T1 is loaded, one-shot output on PB7 11 = continuous interrupts, square wave output on PB7 Timer 1 One-Shot Mode This allows generation of a single interrupt for each Timer load operation. In addition, Timer 1 can be programmed to produce a single negative pulse on PB7. To generate a single i